作者：FPGA技术实战
7系列FPGA SelectIO中HR Bank和HP bank中都有IDELAYE2模块，其在SelectIO路径位置如下图所示。
Kintex-7器件DC and AC 开关特性手册中介绍了IDELAY延迟分辨率及最大工作时钟，如下表所示。
根据上图延迟分辨率，例如当参考时钟为200MHz时，根据公式计算：
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
IDELAYE2_inst (
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output
.C(C), // 1-bit input: Clock input
.CE(CE), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
.DATAIN(DATAIN), // 1-bit input: Internal delay data input
.IDATAIN(IDATAIN), // 1-bit input: Data input from the I/O
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
.LD(LD), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
);
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
.RDY(RDY), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(RST) // 1-bit input: Active high reset input
);
5. IDELAYE2原句工程源码与仿真测试
5.1 开发环境
硬件平台：XC7Z035FFG676-2
软件环境：Vivado 2017.4 仿真软件：Vivado Simulator
IDELAYE2工程源码：
module IDELAYE2_Test(
input clk_in_50M, //时钟
input rst_n, //复位
input ld,
input ce,
input inc,
input [4:0] tap_value_in, //设置延迟抽头系数
input data_in_from_pins, //输入Pins数据
output [4:0] tap_value_out,
output delay_ctrl_rdy, //IDELAYCTRL 延迟校准ready信号
output data_in_from_pins_delay //输出Pins延迟数据
);
wire pll_locked;
wire clk_200M;
wire clk_50M;
wire REFCLK;
wire RST;
//IDELAYCTRL 时钟及复位
assign REFCLK = clk_200M;
assign RST = pll_locked ? ~rst_n : 1'b1; //复位DELAYCTRL原句
// ======== 例化PLL时钟 ========
clk_wiz_0 pll0
(
// Clock out ports
.clk_out1(clk_200M), // output clk_out1
.clk_out2(clk_50M), // output clk_out2
// Status and control signals
.locked(pll_locked), // output locked
// Clock in ports
.clk_in1(clk_in_50M)); // input clk_in1
// ======== 例化 IDELAYCTRL 和 IDELAYE2 ========
(* IODELAY_GROUP = "IODELAY_Test_IO" *) // 指定关联的IDELAY/ODELAY和IDELAYCTRL的组名
IDELAYCTRL IDELAYCTRL_inst (
.RDY(delay_ctrl_rdy), // 1-bit output: Ready output
.REFCLK(REFCLK), // 1-bit input: Reference clock input
.RST(RST) // 1-bit input: Active high reset input
);
(* IODELAY_GROUP = "IODELAY_Test_IO" *) //指定关联的IDELAY/ODELAY和IDELAYCTRL的组名
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE 操作模式选择
.IDELAY_VALUE(5'd9), // Input delay tap setting (0-31) 固定延迟Tap
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).时钟常量
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
)
IDELAYE2_inst (
.CNTVALUEOUT(tap_value_out), // 5-bit output: Counter value output
.DATAOUT(data_in_from_pins_delay), // 1-bit output: Delayed data output
.C(clk_50M), // 1-bit input: Clock input,该时钟用于驱动IDELAYE2内部控制信号
.CE(ce), // 1-bit input: Active high enable increment/decrement input
.CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
.CNTVALUEIN(tap_value_in), // 5-bit input: Counter value input
.DATAIN(1'b0), // 1-bit input: Internal delay data input
.IDATAIN(data_in_from_pins), // 1-bit input: Data input from the I/O
.INC(inc), // 1-bit input: Increment / Decrement tap delay input
.LD(ld), // 1-bit input: Load IDELAY_VALUE input
.LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
.REGRST(RST) // 1-bit input: Active-high reset tap-delay input
);
IDELAYE2 Testbench部分源码：
initial begin
//1. 测试IDELAYE2模式为"FIXED"--------.IDELAY_TYPE("FIXED")
#10000 data_in_from_pins = 1'b1; //输入脉冲
#20 data_in_from_pins = 1'b0;
//2.测试IDELAYE2模式为"VARIABLE"--------.IDELAY_TYPE("VARIABLE")
#200 ld = 1'b1; //控制信号
#50 ld = 1'b0;
#20 //"VARIABLE"模式下，使能ce和inc，Tap=Current Value + 1
ce = 1'b1;
inc = 1'b1;
#40
ce = 1'b0;
inc = 1'b0;
#20 data_in_from_pins = 1'b1; //输入数据
#20 data_in_from_pins = 1'b0;
//3.测试IDELAYE2模式为"VAR_LOAD"--------.IDELAY_TYPE("VAR_LOAD")
#20 tap_value_in = 5'd5; //控制信号
#100 ld = 1'b1; //"VARIABLE"模式下，使能ld，Tap= CNTVALUEIN值
#50 ld = 1'b0;
#20 data_in_from_pins = 1'b1; //输入数据
#20 data_in_from_pins = 1'b0;
#20 //“VAR_LOAD”模式下，使能ce和inc，Tap=Current Value + 1
ce = 1'b1;
inc = 1'b1;
#40
ce = 1'b0;
inc = 1'b0;
#20 data_in_from_pins = 1'b1; //输入数据
#20 data_in_from_pins = 1'b0;
end
5.3 仿真结果
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE 操作模式选择
.IDELAY_VALUE(5'd9), // Input delay tap setting (0-31) 固定延迟Tap
.IDELAY_TYPE("VARIABLE"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE 操作模式选择
.IDELAY_VALUE(5'd9), // Input delay tap setting (0-31) 固定延迟Tap
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE 操作模式选择
.IDELAY_VALUE(5'd9), // Input delay tap setting (0-31) 固定延迟Tap
.IDELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE 操作模式选择
.IDELAY_VALUE(5'd9), // Input delay tap setting (0-31) 固定延迟Tap
data_in_from_pins_delay信号延迟：TapDelayTime=600ps+78ps*6=1068ps.
