本文转载自: 无界逻辑(微信号:wujieluoji)微信公众号
我们开发FPGA,需要使用硬件描述语言(Hardware Description Language),简称HDL。当前使用最广泛的硬件描述逻辑功能语言是verilog,VHDL和是ystemverilg也有部分工程师在坚持使用。
HDL会涉及到标识符,标识符适用于定义常数,变量,信号,端口,子模块或者参数宏的名称。如何给标识符起名字,特别关键,至关重要,看到标识符,就应该知道这个标识符的内在含义。方便后来者或者以后对代码的阅读理解。
针对参数,推荐采用P_PARAMETER的命名方式,大写,P_前缀。
针对宏定义,推荐采用M_MCRO的命名方式,大写,M_前缀。
而对信号命名和模块命名,三字经法和驼峰法比较常用。
驼峰法,又分为小驼峰和大驼峰,比较常用。
如下图所示小驼峰命名法。
此处推荐”三字经“的写法,即利用三个左右的字母缩写加下划线级联的方式命名。
如:dma_len,atr_din_rdy
常用的缩写如下表:
全拼 | 缩写 |
acknowledge | ack |
addition | add |
address | addr |
almost empty | aempty |
almost full | afull |
answer | ans |
argument | arg |
array | arr |
asynchrounus | async |
audio | aud |
average | avg |
back | bk |
block | blk |
blue | blu |
bottom | bot |
buffer | buff |
calculate | calc |
capture | capt |
change | chg |
channel | ch |
character | char |
check | chk |
chip select | cs |
clock | clk |
clear | clr |
column | col |
combine | cmb |
command | cmd |
compare | cmp |
configure | cfg |
consume | csm |
control | ctrl |
count | cnt |
current | curr |
data | dat |
debug | dbg |
decode/decoder | dec |
define | def |
delay | dly |
delay1cycle | _d1 |
delay2cycle | _d2 |
delay3cycle | _d3 |
delete | del |
destination | dst |
detect | det |
device | dev |
different | diff |
directory | dir |
display | disp |
division/divide | div |
document | doc |
double | dbl |
double buffer | drop |
dynamic | dyna |
empty | ept |
enable | en |
encode/eoncoder | enc |
environment | env |
error | err |
ethernet | eth |
execute | exec |
extend | ext |
feed back | fb |
filter | flt |
finish | fin |
finite state machine | fsm |
first | 1st |
flag | flg |
frame | frm |
frame per second | fps |
frequency | freq |
full | ful |
function | fun |
generate | gen |
global | glb |
green | gre |
ground | gnd |
group | grp |
header | hdr |
heartbeat | htbt |
height | ht |
high | _h |
identification | id |
image | img |
implement | impl |
increment | inc |
index | idx |
information | info |
initalize | init |
inout | io_ |
input | i_ |
input & output | io |
insert | ins |
interface | if |
interrupt | int |
iteration | itr |
layer | lay |
length | len |
level | lev |
library | lib |
line | ln |
link | lnk |
list | lst |
local | loc |
logical | log |
low | _l |
make | mk |
manager | mgr |
master | mst |
match | mat |
maximum | max |
memory | mem |
message | msg |
micro block | mb |
middle | mid |
minimum | min |
mouse & keyboard | mk |
multiplication | mul |
negedge/falling | neg |
negitivt | _n |
next | nxt |
number | num |
object | obj |
operand | op |
operator | optr |
optimization | opt |
origin/original | org |
output | o_ |
over flow | of |
package | pkg |
packet | pkt |
padding | pad |
parameter | para |
password | psw |
payload type | pt |
physical | phy |
picture | pic |
point | pnt |
pointer | ptr |
posedge/raising | pos |
position | pos |
positive | _p |
power | pwr |
previous | pre |
process/procedure | proc |
public | pub |
read | rd |
read only | ro |
read write | rw |
ready | rdy |
receive | rx |
record | rcd |
red | r |
region | rgn |
register | reg |
release | rls |
request | req |
reset | rst |
result | res |
return | ret |
screen | srcn |
second | 2nd |
segment | seg |
select | sel |
server | svr |
signaling | sig |
slave | slv |
slice | slc |
source | src |
stack | stk |
standard | std |
start | st |
state | s_ |
status | stat |
stream | strm |
string | str |
subtraction | sub |
summation | sum |
synchronization | syn |
system | sys |
table | tbl |
temporary | tmp |
test | tst |
text | txt |
third | 3rd |
threshold | th |
time stamp | ts |
total | tot |
transmitter | tx |
triple | tri |
tristate | t_ |
update | upd |
upgrade | upg |
user interface | ui |
utility | util |
valid | vld |
value | val |
variable | var |
variable length code | vlc |
version | ver |
vertical synchronous | vsync |
video | vid |
wide/width | wd |
window | wnd |
wire | w_ |
write | wr |
cyclic redundancy check | crc |
需要特别注意的是,命名一定要避免使用verilog,systemverilog的保留字。
还有哪些常用的缩略语,请推荐给作者。