Xilinx FPGA 源语:xpm_fifo_async FIFO介绍

周三, 1 六月 2022 - 15:12

使用Xilinx源语来描述FIFO具有很多好处，可以通过Xilinx Vivado 工具的Langguage Templates查看源语定义。
<center><img src="http://xilinx.eetrend.com/files/2022-06/wen_zhang_/100560857-255911-01…; alt=""></center>

xpm_fifo_async #(

.CDC_SYNC_STAGES(2), // DECIMAL

.DOUT_RESET_VALUE("0"), // String

.ECC_MODE("no_ecc"), // String

.FIFO_MEMORY_TYPE("auto"), // String

.FIFO_READ_LATENCY(1), // DECIMAL

.FIFO_WRITE_DEPTH(2048), // DECIMAL

.FULL_RESET_VALUE(0), // DECIMAL

.PROG_EMPTY_THRESH(10), // DECIMAL

.PROG_FULL_THRESH(10), // DECIMAL

.RD_DATA_COUNT_WIDTH(1), // DECIMAL

.READ_DATA_WIDTH(32), // DECIMAL

.READ_MODE("std"), // String

.RELATED_CLOCKS(0), // DECIMAL

.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages

.USE_ADV_FEATURES("0707"), // String

.WAKEUP_TIME(0), // DECIMAL

.WRITE_DATA_WIDTH(32), // DECIMAL

.WR_DATA_COUNT_WIDTH(1) // DECIMAL

)

xpm_fifo_async_inst (

.almost_empty(almost_empty), // 1-bit output: Almost Empty : When asserted, this signal indicates that

// only one more read can be performed before the FIFO goes to empty.

.almost_full(almost_full), // 1-bit output: Almost Full: When asserted, this signal indicates that

// only one more write can be performed before the FIFO is full.

.data_valid(data_valid), // 1-bit output: Read Data Valid: When asserted, this signal indicates

// that valid data is available on the output bus (dout).

.dbiterr(dbiterr), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected

// a double-bit error and data in the FIFO core is corrupted.

.dout(dout), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven

// when reading the FIFO.

.empty(empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the

// FIFO is empty. Read requests are ignored when the FIFO is empty,

// initiating a read while empty is not destructive to the FIFO.

.full(full), // 1-bit output: Full Flag: When asserted, this signal indicates that the

// FIFO is full. Write requests are ignored when the FIFO is full,

// initiating a write when the FIFO is full is not destructive to the

// contents of the FIFO.

.overflow(overflow), // 1-bit output: Overflow: This signal indicates that a write request

// (wren) during the prior clock cycle was rejected, because the FIFO is

// full. Overflowing the FIFO is not destructive to the contents of the

// FIFO.

.prog_empty(prog_empty), // 1-bit output: Programmable Empty: This signal is asserted when the

// number of words in the FIFO is less than or equal to the programmable

// empty threshold value. It is de-asserted when the number of words in

// the FIFO exceeds the programmable empty threshold value.

.prog_full(prog_full), // 1-bit output: Programmable Full: This signal is asserted when the

// number of words in the FIFO is greater than or equal to the

// programmable full threshold value. It is de-asserted when the number of

// words in the FIFO is less than the programmable full threshold value.

.rd_data_count(rd_data_count), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the

// number of words read from the FIFO.

.rd_rst_busy(rd_rst_busy), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read

// domain is currently in a reset state.

.sbiterr(sbiterr), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected

// and fixed a single-bit error.

.underflow(underflow), // 1-bit output: Underflow: Indicates that the read request (rd_en) during

// the previous clock cycle was rejected because the FIFO is empty. Under

// flowing the FIFO is not destructive to the FIFO.

.wr_ack(wr_ack), // 1-bit output: Write Acknowledge: This signal indicates that a write

// request (wr_en) during the prior clock cycle is succeeded.

.wr_data_count(wr_data_count), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates

// the number of words written into the FIFO.

.wr_rst_busy(wr_rst_busy), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO

// write domain is currently in a reset state.

.din(din), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when

// writing the FIFO.

.injectdbiterr(injectdbiterr), // 1-bit input: Double Bit Error Injection: Injects a double bit error if

// the ECC feature is used on block RAMs or UltraRAM macros.

.injectsbiterr(injectsbiterr), // 1-bit input: Single Bit Error Injection: Injects a single bit error if

// the ECC feature is used on block RAMs or UltraRAM macros.

.rd_clk(rd_clk), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free

// running clock.

.rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this

// signal causes data (on dout) to be read from the FIFO. Must be held

// active-low when rd_rst_busy is active high.

.rst(rst), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be

// unstable at the time of applying reset, but reset must be released only

// after the clock(s) is/are stable.

.sleep(sleep), // 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo

// block is in power saving mode.

.wr_clk(wr_clk), // 1-bit input: Write clock: Used for write operation. wr_clk must be a

// free running clock.

.wr_en(wr_en) // 1-bit input: Write Enable: If the FIFO is not full, asserting this

// signal causes data (on din) to be written to the FIFO. Must be held

// active-low when rst or wr_rst_busy is active high.

);

使用XILINX源语来描述FIFO具有很多好处，可以通过XILINX VIVADO 工具的Langguage Templates查看源语定义。

xpm_fifo_async #(

.CDC_SYNC_STAGES(2), // DECIMAL

.DOUT_RESET_VALUE("0"), // String

.ECC_MODE("no_ecc"), // String

.FIFO_MEMORY_TYPE("auto"), // String

.FIFO_READ_LATENCY(1), // DECIMAL

.FIFO_WRITE_DEPTH(2048), // DECIMAL

.FULL_RESET_VALUE(0), // DECIMAL

.PROG_EMPTY_THRESH(10), // DECIMAL

.PROG_FULL_THRESH(10), // DECIMAL

.RD_DATA_COUNT_WIDTH(1), // DECIMAL

.READ_DATA_WIDTH(32), // DECIMAL

.READ_MODE("std"), // String

.RELATED_CLOCKS(0), // DECIMAL

.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages

.USE_ADV_FEATURES("0707"), // String

.WAKEUP_TIME(0), // DECIMAL

.WRITE_DATA_WIDTH(32), // DECIMAL

.WR_DATA_COUNT_WIDTH(1) // DECIMAL

)

xpm_fifo_async_inst (

.almost_empty(almost_empty), // 1-bit output: Almost Empty : When asserted, this signal indicates that

// only one more read can be performed before the FIFO goes to empty.

.almost_full(almost_full), // 1-bit output: Almost Full: When asserted, this signal indicates that

// only one more write can be performed before the FIFO is full.

.data_valid(data_valid), // 1-bit output: Read Data Valid: When asserted, this signal indicates

// that valid data is available on the output bus (dout).

.dbiterr(dbiterr), // 1-bit output: Double Bit Error: Indicates that the ECC decoder detected

// a double-bit error and data in the FIFO core is corrupted.

.dout(dout), // READ_DATA_WIDTH-bit output: Read Data: The output data bus is driven

// when reading the FIFO.

.empty(empty), // 1-bit output: Empty Flag: When asserted, this signal indicates that the

// FIFO is empty. Read requests are ignored when the FIFO is empty,

// initiating a read while empty is not destructive to the FIFO.

.full(full), // 1-bit output: Full Flag: When asserted, this signal indicates that the

// FIFO is full. Write requests are ignored when the FIFO is full,

// initiating a write when the FIFO is full is not destructive to the

// contents of the FIFO.

.overflow(overflow), // 1-bit output: Overflow: This signal indicates that a write request

// (wren) during the prior clock cycle was rejected, because the FIFO is

// full. Overflowing the FIFO is not destructive to the contents of the

// FIFO.

.prog_empty(prog_empty), // 1-bit output: Programmable Empty: This signal is asserted when the

// number of words in the FIFO is less than or equal to the programmable

// empty threshold value. It is de-asserted when the number of words in

// the FIFO exceeds the programmable empty threshold value.

.prog_full(prog_full), // 1-bit output: Programmable Full: This signal is asserted when the

// number of words in the FIFO is greater than or equal to the

// programmable full threshold value. It is de-asserted when the number of

// words in the FIFO is less than the programmable full threshold value.

.rd_data_count(rd_data_count), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the

// number of words read from the FIFO.

.rd_rst_busy(rd_rst_busy), // 1-bit output: Read Reset Busy: Active-High indicator that the FIFO read

// domain is currently in a reset state.

.sbiterr(sbiterr), // 1-bit output: Single Bit Error: Indicates that the ECC decoder detected

// and fixed a single-bit error.

.underflow(underflow), // 1-bit output: Underflow: Indicates that the read request (rd_en) during

// the previous clock cycle was rejected because the FIFO is empty. Under

// flowing the FIFO is not destructive to the FIFO.

.wr_ack(wr_ack), // 1-bit output: Write Acknowledge: This signal indicates that a write

// request (wr_en) during the prior clock cycle is succeeded.

.wr_data_count(wr_data_count), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates

// the number of words written into the FIFO.

.wr_rst_busy(wr_rst_busy), // 1-bit output: Write Reset Busy: Active-High indicator that the FIFO

// write domain is currently in a reset state.

.din(din), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when

// writing the FIFO.

.injectdbiterr(injectdbiterr), // 1-bit input: Double Bit Error Injection: Injects a double bit error if

// the ECC feature is used on block RAMs or UltraRAM macros.

.injectsbiterr(injectsbiterr), // 1-bit input: Single Bit Error Injection: Injects a single bit error if

// the ECC feature is used on block RAMs or UltraRAM macros.

.rd_clk(rd_clk), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free

// running clock.

.rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this

// signal causes data (on dout) to be read from the FIFO. Must be held

// active-low when rd_rst_busy is active high.

.rst(rst), // 1-bit input: Reset: Must be synchronous to wr_clk. The clock(s) can be

// unstable at the time of applying reset, but reset must be released only

// after the clock(s) is/are stable.

.sleep(sleep), // 1-bit input: Dynamic power saving: If sleep is High, the memory/fifo

// block is in power saving mode.

.wr_clk(wr_clk), // 1-bit input: Write clock: Used for write operation. wr_clk must be a

// free running clock.

.wr_en(wr_en) // 1-bit input: Write Enable: If the FIFO is not full, asserting this

// signal causes data (on din) to be written to the FIFO. Must be held

// active-low when rst or wr_rst_busy is active high.

);

UG974中有关于xpm_fifo_async的具体描述，在配套工程的uisrc/doc路径下，已经提供了下载好的“ug974-vivado-ultrascale-libraries.pdf”。
<center><img src="http://xilinx.eetrend.com/files/2022-06/wen_zhang_/100560857-255913-02…; alt=""></center>

接口描述如下(摘录于ug974)：

<body>
<table border="1" cellspacing="0">
<tbody>
<tr>
<td>Port</td>
<td>Direction</td>
<td>Function
 </td>
</tr>
<tr>
<td>almost_empty</td>
<td>Output</td>
<td>Almost Empty : When asserted,this signal indicates that only one more read can be performed before the FIFO goes to empty.</td>
</tr>
<tr>
<td>almost_full</td>
<td>Output</td>
<td>Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full.</td>
</tr>
<tr>
<td>data_valid</td>
<td>Output</td>
<td>Read Data Valid: When asserted,this signal indicates that valid data is available on the output bus (dout).</td>
</tr>
<tr>
<td>dbiterr</td>
<td>Output</td>
<td>Double Bit Error: Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted.</td>
</tr>
<tr>
<td>Din[WRITE_DATA_WIDTH-1 :0]</td>
<td>Input</td>
<td>Write Data: The input data bus used when writing the FIFO.</td>
</tr>
<tr>
<td>dout</td>
<td>Output</td>
<td>Read Data: The output data bus is driven when reading the FIFO</td>
</tr>
<tr>
<td>empty</td>
<td>Output</td>
<td>Empty Flag: When asserted, this signal indicates that the FIFO is empty.
Read requests are ignored when the FIFO is empty, initiating a read while empty is not destructive to the FIFO.</td>
</tr>
<tr>
<td>full</td>
<td>Output</td>
<td>Full Flag: When asserted, this signal indicates that the FIFO is
full.
Write requests are ignored when the FIFO is full, initiating a write when the FIFO is full is not destructive to the contents of the FIFO.</td>
</tr>
<tr>
<td>injectdbiterr</td>
<td>Input</td>
<td>Double Bit Error Injection: Injects a double bit error if the ECC feature is used on block RAMs or UltraRAM macros.</td>
</tr>
<tr>
<td>injectsbiterr</td>
<td>Input</td>
<td>Single Bit Error Injection: Injects a single bit error if the ECC feature is used on block RAMs or UltraRAM macros.</td>
</tr>
<tr>
<td>overflow</td>
<td>Output</td>
<td>Overflow: This signal indicates that a write request (wren) during the prior clock cycle was rejected, because the FIFO is full. Overflowing the FIFO is not destructive to the contents of the FIFO.</td>
</tr>
<tr>
<td>prog_empty</td>
<td> </td>
<td>Programmable Empty: This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value.
It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value.</td>
</tr>
<tr>
<td>prog_full</td>
<td> </td>
<td>Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value.
It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value.</td>
</tr>
<tr>
<td>rd_clk</td>
<td>Input</td>
<td>Read clock: Used for read operation. rd_clk must be a free running clock.</td>
</tr>
<tr>
<td>rd_data_coun[RD_DATA_COUNT_WIDTH-1:0]</td>
<td>Output</td>
<td>Read Data Count: This bus indicates the number of words read from the FIFO.</td>
</tr>
<tr>
<td>rd_en</td>
<td>Input</td>
<td>Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read from the FIFO.
Must be held active-low when rd_rst_busy is active high.</td>
</tr>
<tr>
<td>rd_rst_busy</td>
<td>Output</td>
<td>Read Reset Busy: Active-High indicator that the FIFO read domain is currently in a reset state.</td>
</tr>
<tr>
<td>rst</td>
<td>Input</td>
<td>Reset: Must be synchronous to wr_clk. Must be applied only when wr_clk is stable and free-running.</td>
</tr>
<tr>
<td>sbiterr</td>
<td>Output</td>
<td>Single Bit Error: Indicates that the ECC decoder detected and fixed a single-bit error.</td>
</tr>
<tr>
<td>sleep</td>
<td>Input</td>
<td>Dynamic power saving: If sleep is High, the memory/fifo block is in power saving mode.</td>
</tr>
<tr>
<td>underflow</td>
<td>Output</td>
<td>Underflow: Indicates that the read request (rd_en) during the previous clock cycle was rejected because the FIFO is empty.Under flowing the FIFO is not destructive to the FIFO.</td>
</tr>
<tr>
<td>wr_ack</td>
<td>Output</td>
<td>Write Acknowledge: This signal indicates that a write request(wr_en) during the prior clock cycle is succeeded.</td>
</tr>
<tr>
<td>wr_clk</td>
<td>Input</td>
<td>Write clock: Used for write operation. wr_clk must be a free running clock.</td>
</tr>
<tr>
<td>wr_data_coun[WR_DATA_COUNT_WIDTH-1:0]</td>
<td>Output</td>
<td>Write Data Count: This bus indicates the number of words written into the FIFO.</td>
</tr>
<tr>
<td>wr_en</td>
<td>Input</td>
<td>Write Enable: If the FIFO is not full, asserting this signal causes data (on din) to be written to the FIFO.
Must be held active-low when rst or wr_rst_busy is active high.</td>
</tr>
<tr>
<td>wr_rst_busy</td>
<td>Output</td>
<td>Write Reset Busy: Active-High indicator that the FIFO write domain is currently in a reset state.</td>
</tr>
</tbody>
</table>
</body>

接口参数描述如下：

<body>
<table border="1" cellspacing="0">
<tbody>
<tr>
<td>Attribute</td>
<td>Allowed Values</td>
<td>Default</td>
<td>Description</td>
</tr>
<tr>
<td>CDC_SYNC_STAGES</td>
<td>2 to 8</td>
<td>2</td>
<td>Specifies the number of synchronization stages on the CDC path Must be < 5 if FIFO_WRITE_DEPTH = 16</td>
</tr>
<tr>
<td>DOUT_RESET_VALUE</td>
<td>String</td>
<td>"0"</td>
<td>Reset value of read data path.</td>
</tr>
<tr>
<td>ECC_MODE</td>
<td>"no_ecc",
"en_ecc"</td>
<td>"no_ecc"</td>
<td>• "no_ecc" - Disables ECC
• "en_ecc" - Enables both ECC Encoder and Decoder</td>
</tr>
<tr>
<td>FIFO_MEMORY_TYPE</td>
<td>"auto",
"block",
"distributed"</td>
<td>"auto"</td>
<td>Designate the fifo memory primitive(resource type) to use.
• "auto" - Allow Vivado Synthesis to choose
• "block" - Block RAM FIFO
• "distributed" - Distributed RAM FIFO</td>
</tr>
<tr>
<td>FIFO_READ_LATENCY</td>
<td>0 to 10</td>
<td>1</td>
<td>Number of output register stages in the read data path.
If READ_MODE = "fwft", then the only applicable value is 0.</td>
</tr>
<tr>
<td>FIFO_WRITE_DEPTH</td>
<td>16 to 4194304</td>
<td>2048</td>
<td>Defines the FIFO Write Depth, must be power of two.
• In standard READ_MODE, the effective depth = FIFO_WRITE_DEPTH - 1
• In First - Word - Fall – Through READ_MODE, the effective depth =FIFO_WRITE_DEPTH + 1</td>
</tr>
<tr>
<td>FULL_RESET_VALUE</td>
<td>0 to 1</td>
<td>0</td>
<td>Sets full, almost_full and prog_full to FULL_RESET_VALUE during reset</td>
</tr>
<tr>
<td>PROG_EMPTY_THRESH</td>
<td>3 to 4194301</td>
<td>10</td>
<td>Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted.
• Min_Value = 3 + (READ_MODE_VAL * 2)
• Max_Value = (FIFO_WRITE_DEPTH - 3) -(READ_MODE_VAL * 2)
If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1.
NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.</td>
</tr>
<tr>
<td>PROG_FULL_THRESH</td>
<td>5 to 4194301</td>
<td>10</td>
<td>Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.
• Min_Value = 3 + (READ_MODE_VAL* 2 * (FIFO_WRITE_DEPTH/ FIFO_READ_DEPTH)) + CDC_SYNC_STAGES
• Max_Value = (FIFO_WRITE_DEPTH- 3) - (READ_MODE_VAL *2 * (FIFO_WRITE_DEPTH /FIFO_READ_DEPTH))
If READ_MODE = "std", then READ_MODE_VAL = 0; Otherwise READ_MODE_VAL = 1. NOTE: The default threshold value is dependent on default FIFO_WRITE_DEPTH value. If FIFO_WRITE_DEPTH value is changed, ensure the threshold value is within the valid range though the programmable flags are not used.</td>
</tr>
<tr>
<td>RD_DATA_COUNT_WIDTH</td>
<td>1 to 23</td>
<td>1</td>
<td>Specifies the width of rd_data_count FIFO_READ_DEPTH = FIFO_WRITE_DEPTH *WRITE_DATA_WIDTH / READ_DATA_WIDTH</td>
</tr>
<tr>
<td>READ_DATA_WIDTH</td>
<td>1 to 4096</td>
<td>32</td>
<td>Defines the width of the read data port, dout</td>
</tr>
<tr>
<td>READ_MODE</td>
<td>"std", "fwft"</td>
<td>"std"</td>
<td>• "std" - standard read mode
• "fwft" - First - Word - Fall – Through read mode</td>
</tr>
<tr>
<td>RELATED_CLOCKS</td>
<td>0 to 1</td>
<td>0</td>
<td>Specifies if the wr_clk and rd_clk are related having the same source but different clock ratios</td>
</tr>
<tr>
<td>USE_ADV_FEATURES</td>
<td>String</td>
<td>"0707"</td>
<td>Enables data_valid, almost_empty,rd_data_count, prog_empty, underflow,wr_ack, almost_full, wr_data_count, prog_full,overflow features.
• Setting USE_ADV_FEATURES[0] to 1 enables overflow flag; Default value of this bit is 1
• Setting USE_ADV_FEATURES[1] to 1 enables prog_full flag; Default value of this bit is 1
• Setting USE_ADV_FEATURES[2] to 1 enables wr_data_count; Default value of this bit is 1
• Setting USE_ADV_FEATURES[3] to 1 enables almost_full flag; Default value of this bit is 0
• Setting USE_ADV_FEATURES[4] to 1 enables wr_ack flag; Default value of this bit is 0
• Setting USE_ADV_FEATURES[8] to 1 enables underflow flag; Default value of this bit is 1
• Setting USE_ADV_FEATURES[9] to 1 enables prog_empty flag; Default value of this bit is 1
• Setting USE_ADV_FEATURES[10] to 1 enables rd_data_count; Default value of this bit is 1
• Setting USE_ADV_FEATURES[11] to 1 enables almost_empty flag; Default value of this bit is 0
• Setting USE_ADV_FEATURES[12] to 1 enables data_valid flag; Default value of this bit is 0</td>
</tr>
<tr>
<td>WAKEUP_TIM</td>
<td>0 to 2</td>
<td> </td>
<td>• 0 - Disable sleep
• 2 - Use Sleep Pin</td>
</tr>
<tr>
<td>WR_DATA_COUNT_WIDTH</td>
<td>1 to 23</td>
<td>1</td>
<td>Specifies the width of wr_data_count</td>
</tr>
<tr>
<td>WRITE_DATA_WIDTH</td>
<td>1 to 4096</td>
<td>32</td>
<td>Defines the width of the write data port, din</td>
</tr>
</tbody>
</table>
</body>