FPGA中有符号数和无符号数的加法运算
首先定义一个B比特的二进制数：
verilog HDL表示正数就按一般的规则即可，这里主要讲如何表示负数？
无符号数
将（1）转换成十进制为：
有符号数
有符号数则指所有二进制数均是补码形式的整数。
首先声明端口时增加signed关键字即可。对于B比特的二进制数据，装换成十进制数为：
//verilog HDL
module top(
input signed [3:0] a,
input signed [3:0] b,
output signed [3:0] sum,
output carry
);
assign {carry,sum} = a + b;
endmodule
//simulate verilog
`timescale 1 ns /1 ps
module top_tb;
reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
wire carry;
initial begin
a = 4'b0000;
b = 4'b0000;
#100;
a = 4'b0001;
b = 4'b0001;
#100;
a = 4'b0010;
b = 4'b0010;
#100;
a = 4'b0011;
b = 4'b0011;
#100;
a = 4'b0100;
b = 4'b0100;
#100;
a = 4'b0101;
b = 4'b0101;
#100;
a = 4'b0110;
b = 4'b0110;
#100;
a = 4'b0111;
b = 4'b0111;
#100;
a = 4'b1000;
b = 4'b1000;
#100;
a = 4'b1001;
b = 4'b1001;
#100;
a = 4'b1010;
b = 4'b1010;
#100;
a = 4'b1011;
b = 4'b1011;
#100;
a = 4'b1100;
b = 4'b1100;
#100;
a = 4'b1101;
b = 4'b1101;
#100;
a = 4'b1110;
b = 4'b1110;
#100;
a = 4'b1111;
b = 4'b1111;
#100;
end
top U1(
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
endmodule
仿真波形：
有图可知:
后八种情况是溢出至进位。
对于B比特的二进制，有符号整数的范围：
-2^(B-1)~2^(B-1)-1
文章转载自：tutu_1583
